github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 07:10:19 +00:00
Code Issues Releases Wiki Activity
14,785 Commits 134 Branches 66 Tags
6462cd2167ac4831035c8df834a8bf4d608e9e9c
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00