github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-26 20:28:22 +00:00
Code Issues Releases Wiki Activity
6,679 Commits 132 Branches 66 Tags
64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00