Adam Izraelevitz
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794cec0016
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More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
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2017-02-13 11:17:53 -08:00 |
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Adam Izraelevitz
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f77dc3bacc
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Bugfix: include assign to write-mask
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2016-11-18 11:49:26 -08:00 |
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Clifford Wolf
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e01382739d
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More progress in FIRRTL back-end
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2016-11-18 02:41:29 +01:00 |
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Clifford Wolf
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c051115e03
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Progress in FIRRTL back-end
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2016-11-18 00:32:35 +01:00 |
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Clifford Wolf
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57966a619f
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Added first draft of FIRRTL back-end
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2016-11-17 23:36:47 +01:00 |
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