github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-29 05:21:15 +00:00
Code Issues Releases Wiki Activity
4,108 Commits 116 Branches 63 Tags
7bd2144d03ae5daffbcddea609d2db7df7b751a2
Commit Graph

2 Commits

Author SHA1 Message Date
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00