github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-07 09:07:09 +00:00
Code Issues Releases Wiki Activity
8,350 Commits 119 Branches 64 Tags
823a08e0d8272e8d48584eecc2d8dc57bdb98a6e
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00