github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-10 02:19:50 +00:00
Code Issues Releases Wiki Activity
1,003 Commits 120 Branches 64 Tags
8a0216bd9f81faf45e1ff463edcc6d82dfa20565
Commit Graph

1 Commits

Author SHA1 Message Date
Clifford Wolf
00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00