1
0
mirror of synced 2026-02-21 15:07:30 +00:00
Commit Graph

4 Commits

Author SHA1 Message Date
Emil J. Tywoniak
ae281720cf tests: remove unstable FPGA synthesis result checks 2025-11-12 11:52:04 +01:00
Anhijkt
ca8af1f8c8 opt_dff: implement simplify_patterns 2025-07-21 14:15:26 +03:00
Emil J. Tywoniak
6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Martin Povišer
6672b6c1b3 quicklogic: Move pp3 tests one level down 2023-12-04 15:52:02 +01:00