github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-26 08:54:54 +00:00
Code Issues Releases Wiki Activity
7,014 Commits 122 Branches 64 Tags
8f503fe3e65ba9be2ef7438b2f4143f88ea8a025
Commit Graph

1 Commits

Author SHA1 Message Date
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00