github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 07:35:21 +00:00
Code Issues Releases Wiki Activity
7,133 Commits 137 Branches 66 Tags
99a7f39084cf4b9cd21e2a1e4f4a842993dfd147
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00