3 Commits

Author	SHA1	Message	Date
Clifford Wolf	7d1088afc4	Add missing .gitignore ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-12-06 07:29:37 +01:00
Ruben Undheim	397dfccb30	Support for SystemVerilog interfaces as a port in the top level module + test case	2018-10-20 11:58:25 +02:00
Ruben Undheim	d5aac2650f	Basic test for checking correct synthesis of SystemVerilog interfaces	2018-10-18 22:40:53 +02:00