github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-25 08:31:37 +00:00
Code Issues Releases Wiki Activity
14,765 Commits 121 Branches 64 Tags
ae7a97cc2d8bb2e92c96b08f83de4fc57e12fe74
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00