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3 Commits

Author SHA1 Message Date
Clifford Wolf
0ac72e759d Add generation of logic cells to EDIF back-end runtest.py 2017-03-19 14:57:40 +01:00
Clifford Wolf
850f8299a9 Fix EDIF: portRef member 0 is always the MSB bit 2017-03-19 14:53:28 +01:00
Clifford Wolf
1390e9a0a7 Add simple EDIF test case generator and checker 2017-03-18 15:00:03 +01:00