github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 15:45:07 +00:00
Code Issues Releases Wiki Activity
10,050 Commits 136 Branches 66 Tags
b74eb598bc7dbf76d3308155a709325b820c4e99
Commit Graph

2 Commits

Author SHA1 Message Date
Marcin Kościelnicki
30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki
ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00