github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-20 14:45:06 +00:00
Code Issues Releases Wiki Activity
9,438 Commits 121 Branches 64 Tags
bbde2419420a86635baf2b730ebe58ed6edca5bb
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00