Lofty
13dea19b06
analogdevices: LUT RAM only on positive edge
2026-01-22 18:32:36 +00:00
Lofty
d263a1f2e7
analogdevices: DSP tweaks
2026-01-22 18:32:36 +00:00
Lofty
c0a894497b
analogdevices: DSP inference
2026-01-22 18:32:36 +00:00
Lofty
de1231c827
analogdevices: remove cells_xtra
2026-01-22 18:32:36 +00:00
Lofty
265436f7a1
analogdevices: timings for t40lp
2026-01-22 18:32:36 +00:00
Lofty
96cf404eb6
analogdevices: use single tech param
2026-01-22 18:32:36 +00:00
Lofty
cf96908545
analogdevices: expreso does not care about clock buffers
2026-01-22 18:32:36 +00:00
Lofty
042374198a
analogdevices: prepare for t40lp timings
2026-01-22 18:32:36 +00:00
Krystine Sherwin
793376fef1
analogdevices: Adding RBRAM2 and -tech
2026-01-22 18:32:36 +00:00
Krystine Sherwin
6df69160b8
analogdevices: (some) Native BRAM
...
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
2026-01-22 18:32:36 +00:00
Krystine Sherwin
ce839d4880
analogdevices: Native LUTRAM primitives
2026-01-22 18:32:36 +00:00
Lofty
32d1025659
analogdevices: LUTRAM config
2026-01-22 18:32:36 +00:00
Lofty
529c7a092f
analogdevices: update timing model
2026-01-22 18:32:36 +00:00
Lofty
c3bd8d0949
analogdevices: user retargeting
2026-01-22 18:32:36 +00:00
Lofty
35b1bf9aba
analogdevices: more housekeeping
2026-01-22 18:32:36 +00:00
Lofty
b0ba89ec5b
analogdevices: remove some extra cells!
2026-01-22 18:32:36 +00:00
Lofty
8ab390f8f0
test suite
2026-01-22 18:32:36 +00:00
Lofty
1b386711f1
synth_analogdevices: remove scopeinfo cells
2026-01-22 18:32:36 +00:00
Lofty
261c41b581
Create synth_analogdevices
2026-01-22 18:32:36 +00:00
