github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-13 03:34:00 +00:00
Code Issues Releases Wiki Activity
12,067 Commits 124 Branches 64 Tags
bfacaddca8a2e113e4bc3d6177612ccdba1555c8
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00