github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-29 13:31:13 +00:00
Code Issues Releases Wiki Activity
15,642 Commits 118 Branches 63 Tags
c6b8f0eed7e1a8eb2d49b89925e7db435f2c0bf9
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00