github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-27 15:18:23 +00:00
Code Issues Releases Wiki Activity
16,223 Commits 147 Branches 67 Tags
c9c53876b47c5fa187d53c8830cd3ee4671d2491
Commit Graph

1 Commits

Author SHA1 Message Date
Gary Wong
5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-07-03 20:51:12 -06:00