github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-21 07:05:05 +00:00
Code Issues Releases Wiki Activity
10,646 Commits 121 Branches 64 Tags
d555454969aed080d345b044eefb20a2ce53eae2
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00