github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-02 12:59:32 +00:00
Code Issues Releases Wiki Activity
10,693 Commits 130 Branches 65 Tags
d6d5c2ef342240bd8adb925055667d140cb8dd29
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00