This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-25 08:31:37 +00:00
Code
Issues
Releases
Wiki
Activity
15,509
Commits
121
Branches
64
Tags
d8fb4da437b9fc1b4e818f8bfac10ded3a1cee15
Commit Graph
1 Commits
Author
SHA1
Message
Date
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00