This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-01 06:00:26 +00:00
Code
Issues
Releases
Wiki
Activity
7,894
Commits
134
Branches
66
Tags
d8fbf88980d6ccd22e2aa3f34c4ff2a39aeed9df
Commit Graph
1 Commits
Author
SHA1
Message
Date
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00