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YosysHQ.yosys
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2026-02-18 05:43:39 +00:00
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df3e6e1ec99a409c7e3d4e381b55cee7031c009a
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3 Commits
Author
SHA1
Message
Date
Clifford Wolf
b72a7e1104
Replace CRLF line endings with LF in de2i.qsf (quartus example)
2017-04-12 16:51:46 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
dh73
c27dcc1e47
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00