github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-30 13:42:32 +00:00
Code Issues Releases Wiki Activity
4,618 Commits 134 Branches 66 Tags
dfb242c905ff10bb4038f080aeb74a820e8fbd00
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00