github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-16 13:02:42 +00:00
Code Issues Releases Wiki Activity
6,465 Commits 126 Branches 64 Tags
eb80d3d43fdb070fe99718501d3b0fbdca61ab8d
Commit Graph

1 Commits

Author SHA1 Message Date
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00