github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-24 08:13:43 +00:00
Code Issues Releases Wiki Activity
12,239 Commits 121 Branches 64 Tags
ec47bf174549f4f2430c08e0d24bb9ba7bd5390d
Commit Graph

1 Commits

Author SHA1 Message Date
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00