Keith Rothman
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3090951d54
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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:02:27 -08:00 |
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Clifford Wolf
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924d9d6e86
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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Clifford Wolf
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8520b7fbe0
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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Clifford Wolf
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1b159bc955
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Added missing ports and parameters to xilinx brams
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2015-02-01 15:42:59 +01:00 |
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Clifford Wolf
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d29d26f882
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Various cleanups in xilinx techlib
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2015-01-18 19:43:54 +01:00 |
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