github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-03 06:40:15 +00:00
Code Issues Releases Wiki Activity
9,065 Commits 134 Branches 66 Tags
fdafb74eb77e33e9fa2b4e591804d1d02c122ff9
Commit Graph

2 Commits

Author SHA1 Message Date
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00