github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 23:27:07 +00:00
Code Issues Releases Wiki Activity
15,305 Commits 139 Branches 66 Tags
fe3adfd960d97ea7ef762efd082346494a9d8c35
Commit Graph

1 Commits

Author SHA1 Message Date
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00