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v0.48

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yosys-0.10

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yosys-0.9

Mono Color

• 9d6b47466f Add RF initialization Miodrag Milanovic 2024-05-17 09:28:07 +02:00
• 7e4aef06e4 Add register file mapping Miodrag Milanovic 2024-05-16 17:15:55 +02:00
• 11449ec493 Cleanup not connected ports Miodrag Milanovic 2024-05-15 15:55:26 +02:00
• f9f68c3cd1 Split sim models into multiple files and implement few Miodrag Milanovic 2024-05-10 11:15:56 +02:00
• 04d3672121 No need for LOC Miodrag Milanovic 2024-05-09 14:01:53 +02:00
• 41ae513d60 support other I/O configurations Miodrag Milanovic 2024-05-07 09:06:10 +02:00
• 34f08bc639 Enable nanoxplore tests Miodrag Milanovic 2024-05-06 15:25:29 +02:00
• 645888cff5 cleanup Miodrag Milanovic 2024-05-06 15:00:06 +02:00
• 9a9190b67d enable dff context initialization Miodrag Milanovic 2024-04-30 13:40:35 +02:00
• dc16bdd85b DFF reset and context must be in sync Miodrag Milanovic 2024-04-30 13:29:03 +02:00
• cb45f8b69d Fixed of mapping and initialization Miodrag Milanovic 2024-04-30 10:35:45 +02:00
• 198fc963ca Add new DFF types, and added "-nodffe" option Miodrag Milanovic 2024-04-29 08:18:04 +02:00
• 0c4bbf7e4b Fix existing DFF mapping and add new types Miodrag Milanovic 2024-04-29 08:06:32 +02:00
• 94675a5e0b Fix dff simulation model Miodrag Milanovic 2024-04-29 08:06:01 +02:00
• 606439b44c do not leave NX_RAM empty to prevent removing it Miodrag Milanovic 2024-04-24 11:28:03 +02:00
• 4cb8e62626 Properly map ff ram Miodrag Milanovic 2024-04-24 11:01:27 +02:00
• 1591d258a9 Made NX_CY model more robust Miodrag Milanovic 2024-04-22 14:06:03 +02:00
• dac4f04460 add latch mapping, and remove aldff for now Miodrag Milanovic 2024-04-19 18:09:47 +02:00
• cf21b48bfd fix co on nx_cy Miodrag Milanovic 2024-04-07 19:38:47 +02:00
• 31f943513b set add_carry property and all inputs to 0 Miodrag Milanovic 2024-03-25 09:23:31 +01:00
• b6f7383736 break long chains Miodrag Milanovic 2024-03-19 17:47:40 +01:00
• ab32dde81b optimized Miodrag Milanovic 2024-03-19 15:22:53 +01:00
• da6a62f3a0 Initial carry chain handling pass Miodrag Milanovic 2024-03-18 13:27:33 +01:00
• 474ed28aee added no-rw-check, and new rfb models Miodrag Milanovic 2024-03-14 08:40:14 +01:00
• a5bfb23b47 start cleaning rams Miodrag Milanovic 2024-03-13 18:19:41 +01:00
• 370517b1e6 IO Miodrag Milanovic 2024-03-13 12:52:40 +01:00
• fa14c600ff commented remainder of primitives Miodrag Milanovic 2024-03-13 11:23:33 +01:00
• 8023f921e3 RAM Miodrag Milanovic 2024-03-13 11:09:02 +01:00
• b202126c76 IOM Miodrag Milanovic 2024-03-13 10:57:58 +01:00
• 71f0984dc9 fixes Miodrag Milanovic 2024-03-13 10:16:09 +01:00
• ef15325dce removed virtual primitive Miodrag Milanovic 2024-03-13 10:08:18 +01:00
• f836de6bcc mark DSPs as TODOs for now Miodrag Milanovic 2024-03-13 10:07:54 +01:00
• 8f42d6dace fifo Miodrag Milanovic 2024-03-13 09:48:16 +01:00
• 012f0e2952 memory blocks Miodrag Milanovic 2024-03-13 09:26:19 +01:00
• 3ed5ea24b2 sortout more blackboxes Miodrag Milanovic 2024-03-12 16:45:46 +01:00
• 0ecc2e597f PLLs Miodrag Milanovic 2024-03-12 15:23:42 +01:00
• 200e1a7bfe more DSP wrappers Miodrag Milanovic 2024-03-12 15:11:11 +01:00
• ce635abc21 NX_DSP/SPLIT Miodrag Milanovic 2024-03-11 15:26:18 +01:00
• 60611b936b CDC_U Miodrag Milanovic 2024-03-11 14:15:30 +01:00
• 815622f685 CDC_L wrappers Miodrag Milanovic 2024-03-11 13:58:15 +01:00
• 827ea11503 start splitting blackboxes and add wrapper techmap Miodrag Milanovic 2024-03-11 13:03:20 +01:00
• cfce7dd2f8 remove soc Miodrag Milanovic 2024-03-11 10:42:14 +01:00
• 9700971a8a just copy LOC Miodrag Milanovic 2024-03-06 14:45:49 +01:00
• 989eef29b2 produce less cells Miodrag Milanovic 2024-03-01 16:19:00 +01:00
• 74289b7339 remove init from sdff Miodrag Milanovic 2024-03-01 15:25:24 +01:00
• 4c1f84a686 add io mapping Miodrag Milanovic 2024-03-01 13:52:11 +01:00
• 65d2ebac9d fix test Miodrag Milanovic 2024-03-01 13:51:56 +01:00
• b0c4add642 Added lutram Lofty 2024-03-01 13:41:25 +01:00
• 5d898ab223 Add blackboxes Miodrag Milanovic 2024-03-01 12:07:20 +01:00
• 8374f0336d add family and ability to disable carry chains Miodrag Milanovic 2024-03-01 11:11:23 +01:00
• b3f59c9820 Add NX_CY Lofty 2024-03-01 11:10:52 +01:00
• b4e9bb0d85 Add FFs and related tests Lofty 2024-03-01 10:55:54 +01:00
• b4a17cccc3 add few more tests Miodrag Milanovic 2024-03-01 10:49:48 +01:00
• 93543bd874 add lut tests Miodrag Milanovic 2024-03-01 10:45:15 +01:00
• 94b6f19cf0 Make lut init match vendor tools Miodrag Milanovic 2024-03-01 10:44:42 +01:00
• 3b48e9df61 Add initial NanoXplore pass Lofty 2024-03-01 10:43:34 +01:00
• ceba889641 Merge pull request #4540 from YosysHQ/clang-11 Miodrag Milanović 2024-08-15 17:39:42 +02:00
• 1eaf4e0790 Bump version github-actions[bot] 2024-08-15 00:17:57 +00:00
• d709177770 test-compile: Downgrade to focal Krystine Sherwin 2024-08-15 09:34:23 +12:00
• a854903ff0 Merge pull request #4537 from povik/libparse-cleanup Martin Povišer 2024-08-14 18:24:51 +02:00
• ab5d6b06b4 read_liberty: Fix omitted helper change Martin Povišer 2024-08-13 20:12:38 +02:00
• 309d80885b read_liberty: Use available gate creation helpers Martin Povišer 2024-08-13 18:44:40 +02:00
• 3057c13a66 Improve libparse encapsulation Martin Povišer 2024-08-13 18:43:31 +02:00
• c35f5e379c Extend liberty tests Martin Povišer 2024-08-13 18:36:31 +02:00
• 78382eaa6f libparse: Adjust whitespace Martin Povišer 2024-08-13 18:08:21 +02:00
• 4b9f452735 Bump version github-actions[bot] 2024-08-13 00:19:11 +00:00
• 8ce6219a34 Merge pull request #4528 from povik/bump-abc Martin Povišer 2024-08-12 15:53:16 +02:00
• bcb995b506 Sync with yosys-experimental branch Martin Povišer 2024-08-08 17:33:54 +02:00
• 77b2ae2e39 Bump version github-actions[bot] 2024-08-08 00:18:08 +00:00
• 4b5beb635f Pull ABC fix Martin Povišer 2024-08-07 17:31:34 +02:00
• ebffe37e4c Bump ABC Martin Povišer 2024-08-07 13:03:27 +02:00
• b1569de537 Merge pull request #4527 from povik/exec-newline Martin Povišer 2024-08-07 13:04:48 +02:00
• 4c3203866f exec: Add missing newline Martin Povišer 2024-08-07 13:02:00 +02:00
• b6ceff2aab peepopt clockgateff: add testcase George Rennie 2024-08-07 09:59:18 +01:00
• 236c69bed4 clk2fflogic: run peepopt -formalclk before processing design George Rennie 2024-08-07 09:59:44 +01:00
• 2cb3b6e9b8 peepopt: add formal only peepopt to rewrite latches to ffs in clock gates George Rennie 2024-08-06 16:32:26 +01:00
• 669f8b18f0 Bump version github-actions[bot] 2024-08-07 00:18:20 +00:00
• d08bf671b2 Next dev cycle Miodrag Milanovic 2024-08-06 09:48:35 +02:00
• 80ba43d262 Release version 0.44 yosys-0.44 Miodrag Milanovic 2024-08-06 09:42:28 +02:00
• e5d8505349 Merge pull request #4523 from YosysHQ/emil/no-lto-lld Miodrag Milanović 2024-08-06 09:08:09 +02:00
• d2b5788674 Bump version github-actions[bot] 2024-08-06 00:18:14 +00:00
• eeecb54532 Makefile: no LTO and lld by default Emil J. Tywoniak 2024-08-05 19:28:09 +02:00
• 01b99972b4 Merge pull request #4518 from YosysHQ/micko/sim_signal_names N. Engelhardt 2024-08-05 15:03:59 +02:00
• 6d98418f3d Set ranges on exported wires in VCD and FST Miodrag Milanovic 2024-08-02 15:23:00 +02:00
• 7e34142965 Run nix build also on macos. Build with more logs Roland Coeurjoly 2024-07-30 22:47:30 +02:00
• 5f85eef3b4 const: string and bits in a variant emil/src-attribute-std-string Emil J. Tywoniak 2024-07-30 19:58:43 +02:00
• c788484679 Bump version github-actions[bot] 2024-07-30 00:18:19 +00:00
• 3e14e67374 Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase Miodrag Milanović 2024-07-29 16:44:13 +02:00
• 498e0498c5 const: represent string constants as string, assert not accessed as bits Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
• 92cac63845 Merge pull request #4344 from widlarizer/emil/keep_hierarchy Emil J 2024-07-29 16:33:08 +02:00
• 405897a971 Update top value that is returned back to hierarchy pass Miodrag Milanovic 2024-07-29 15:50:38 +02:00
• 9f869b265c Merge pull request #4474 from tony-min-1/mchp N. Engelhardt 2024-07-29 15:28:44 +02:00
• 7c3666ff68 Merge pull request #4505 from YosysHQ/micko/ext_register N. Engelhardt 2024-07-29 15:23:31 +02:00
• e21dd292fc Merge pull request #4502 from YosysHQ/emil/build-opt-levels Emil J 2024-07-29 15:13:52 +02:00
• af0c2fa659 Brewfile: add llvm for lld Emil J. Tywoniak 2024-07-29 15:13:24 +02:00
• 051d83205d Merge pull request #4471 from georgerennie/hashlib_primes Emil J 2024-07-29 15:10:22 +02:00
• 61ae9f4e07 Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2 Martin Povišer 2024-07-29 13:58:19 +02:00
• 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter Emil J. Tywoniak 2024-07-29 10:26:02 +02:00
• 49eaa108a5 Merge pull request #4425 from YosysHQ/emil/doc-sigmap Emil J 2024-07-29 10:18:44 +02:00
• 01fd72520f proc_rom: test src attribute on memories Emil J. Tywoniak 2024-07-25 22:09:13 +02:00