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Mono Color

• 9c51ba1b09 Reduce opt_clean parallelism Robert O'Callahan 2026-03-05 20:04:49 +00:00
• 8d8c05b338 Fix OptCleanPass usage of CleanRunContext to avoid constructing extra KeepCache and ParallelDispatchThreadPool Robert O'Callahan 2026-03-05 02:20:58 +00:00
• 32f5044eaf Clarify "Not passing module as function argument" comment Robert O'Callahan 2026-03-04 02:18:48 +00:00
• 70cc2d67fd opt_clean: refactor Emil J. Tywoniak 2026-02-16 10:57:45 +01:00
• 1260fda83a Add 'init' attributes to RTLIL fuzzing Robert O'Callahan 2026-02-05 18:20:31 +00:00
• cdfc586f18 Add unit tests for ConcurrentWorkQueue Robert O'Callahan 2026-02-03 00:02:00 +00:00
• 1e96328ede Add some tests for ShardedHashSet Robert O'Callahan 2026-02-02 23:36:41 +00:00
• 3910d569da Add unit tests for ConcurrentQueue and ThreadPool Robert O'Callahan 2026-02-02 23:16:20 +00:00
• ac55935a68 Add unit-tests for ParallelDispatchThread and friends Robert O'Callahan 2026-02-02 23:04:34 +00:00
• 3603cd52a0 Pass the module Subpool to rmunused_module_signals and parallelize that function Robert O'Callahan 2026-01-28 22:59:44 +00:00
• 7f3b11e56b Add test that connects a wire with init to a constant Robert O'Callahan 2026-02-05 19:23:10 +00:00
• 19a7c8fcf3 Pass the module Subpool to rmunused_module_cells and parallelize that function Robert O'Callahan 2026-01-28 22:59:04 +00:00
• 8e044d1045 Pass the module Subpool to rmunused_module_init and parallelize that function Robert O'Callahan 2026-01-28 22:46:10 +00:00
• a7437c636d Pass the toplevel thread pool to rmunused_module, create a Subpool, and parallelize remove_temporary_cells Robert O'Callahan 2026-01-28 22:06:19 +00:00
• 887c32cb54 Create a toplevel ParallelDispatchThreadPool and parallelize keep_cache_t::scan_module() with it Robert O'Callahan 2026-01-28 21:58:37 +00:00
• 72a21fe01d Introduce RmStats struct to encapsulate removal statistics Robert O'Callahan 2026-01-28 19:27:09 +00:00
• c2bb7d6a82 Make keep_cache_t process all modules up-front instead of on-demand Robert O'Callahan 2026-01-28 19:14:09 +00:00
• b42bb05b63 Parallelize Design::check() Robert O'Callahan 2026-01-29 22:45:10 +00:00
• e2166c4684 Parallelize collect_garbage() Robert O'Callahan 2026-01-29 22:16:46 +00:00
• 5ff7d344c9 Add FfInitVals::set_parallel() method Robert O'Callahan 2026-01-28 18:20:13 +00:00
• fe329a0e14 Add MonotonicFlag Robert O'Callahan 2026-01-28 19:01:43 +00:00
• e71da96314 Add ConcurrentWorkQueue Robert O'Callahan 2026-01-28 19:00:47 +00:00
• ab238c3145 Add ShardedHashSet Robert O'Callahan 2026-01-28 18:59:35 +00:00
• 87521df534 Add ShardedVector Robert O'Callahan 2026-01-28 18:58:09 +00:00
• b079e5721c Add ParallelDispatchThreadPool Robert O'Callahan 2026-01-28 18:52:17 +00:00
• 898a288a99 Add work_pool_size, IntRange, item_range_for_worker, and ThreadIndex Robert O'Callahan 2026-01-28 18:50:23 +00:00
• 13d9fffdb9 Work around std::reverse miscompilation with empty range Robert O'Callahan 2026-01-28 18:16:24 +00:00
• bd7f2d9ba4 Make log_error() work in a Multithreaded context. Robert O'Callahan 2026-01-28 18:14:46 +00:00
• 7af5dbae35 Add IdString::unescape() method Robert O'Callahan 2026-01-28 18:13:12 +00:00
• 6cd66aed47 setundef: rename process loop variable and respect selection in -init mode abhinavputhran 2026-03-05 17:51:01 -05:00
• df283fa1c9 setundef: use selected_processes() per review feedback abhinavputhran 2026-03-05 11:22:00 -05:00
• 4e54853e35 setundef: use selected_processes() per review feedback abhinavputhran 2026-03-05 11:16:07 -05:00
• d9737acc31 gowin: remove lib_whitebox from latch sim cells Justin Zaun 2026-03-02 16:22:33 -10:00
• 9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) Justin Zaun 2026-03-01 16:11:30 -10:00
• 95d738edc0 Merge pull request #5726 from YosysHQ/emil/double-expose-yosys_celltypes Miodrag Milanović 2026-03-05 11:36:36 +00:00
• 629bf3dffd Merge pull request #5630 from apullin/array-assignment Emil J 2026-03-05 11:10:12 +00:00
• 23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes Emil J. Tywoniak 2026-03-05 11:59:20 +01:00
• da83c93673 analogdevices: fix SHIFTX name Lofty 2026-03-04 12:25:11 +00:00
• f3efa51b3e analogdevices: fix SHREG name Lofty 2026-03-04 12:24:53 +00:00
• e2e8245be9 analogdevices: fix MUXF78 name Lofty 2026-03-04 12:24:13 +00:00
• c747466a7a analogdevices: update missed T40LP timings Lofty 2026-03-04 12:16:35 +00:00
• 91740645a9 analogdevices: update T40LP timings Lofty 2026-01-05 14:45:54 +00:00
• 709746b184 analogdevices: update T16FFC timings Lofty 2026-01-05 10:27:46 +00:00
• cd60dd4912 synth_analogdevices: update timing model and tests Lofty 2025-11-10 13:19:12 +00:00
• 241db706e1 analogdevices: double LUT RAM cost Lofty 2025-10-21 18:04:01 +01:00
• 3592d42d3b analogdevices: ignore $assert cells Lofty 2025-10-20 18:23:25 +01:00
• 5d3ed5a418 analogdevices: Extra tests Krystine Sherwin 2025-10-18 17:38:01 +13:00
• f06018306d analogdevices: Fixing up bram Krystine Sherwin 2025-10-18 17:31:54 +13:00
• 95ef0cd788 analogdevices: Add BRAM options Krystine Sherwin 2025-10-18 12:59:55 +13:00
• 8a09cc5463 analogdevices: LUT RAM only on positive edge Lofty 2025-10-18 12:11:18 +01:00
• dea8c275ff analogdevices: DSP tweaks Lofty 2025-10-18 12:10:50 +01:00
• 39cb61615f analogdevices: DSP inference Lofty 2025-10-16 23:33:59 +01:00
• 891b89f60d analogdevices: remove cells_xtra Lofty 2025-10-15 04:55:12 +01:00
• 4954fc980f analogdevices: timings for t40lp Lofty 2025-10-12 12:55:09 +01:00
• 2c3876671b analogdevices: use single tech param Lofty 2025-10-12 11:31:23 +01:00
• 0a2b6a4f21 analogdevices: expreso does not care about clock buffers Lofty 2025-10-12 11:22:46 +01:00
• 6ee0bfa913 analogdevices: prepare for t40lp timings Lofty 2025-10-12 11:17:50 +01:00
• 9dcffc3dbf analogdevices: Adding RBRAM2 and -tech Krystine Sherwin 2025-10-11 12:06:35 +13:00
• 99e26d80b0 analogdevices: (some) Native BRAM Krystine Sherwin 2025-10-08 17:32:46 +13:00
• 9be3cfb3f9 analogdevices: Update lutram.ys test Krystine Sherwin 2025-10-08 14:13:57 +13:00
• 376f746bc9 analogdevices: Native LUTRAM primitives Krystine Sherwin 2025-10-08 14:08:41 +13:00
• 30a03886a5 analogdevices: LUTRAM config Lofty 2025-10-09 04:38:49 +01:00
• ae5325fe53 analogdevices: update timing model Lofty 2025-10-01 20:13:29 +01:00
• c4bec4e8b8 I thought I removed this... Lofty 2025-10-01 12:47:21 +01:00
• 85eb07d14d analogdevices: user retargeting Lofty 2025-09-30 10:02:44 +01:00
• c9f6d7b2d4 analogdevices: more housekeeping Lofty 2025-09-30 10:02:19 +01:00
• f659cbd159 analogdevices: remove some extra cells! Lofty 2025-09-25 15:09:16 +01:00
• 6f205b41f5 test suite Lofty 2025-09-24 20:56:27 +01:00
• 4f2f064262 synth_analogdevices: remove scopeinfo cells Lofty 2025-09-24 16:29:38 +01:00
• d5ea7f7016 Create synth_analogdevices Lofty 2025-09-23 11:08:17 +01:00
• 4caffa7ebd Merge pull request #5725 from yrabbit/disable-wm-2 Lofty 2026-03-05 05:36:28 +00:00
• 6ac8c8cb05 ast: Add support for array-to-array assignment Andrew Pullin 2026-01-23 06:46:21 -08:00
• 26dc01102e GOWIN. Disable read-before-write mode. YRabbit 2026-03-05 09:17:37 +10:00
• 94c789e9c8 setundef: respect selection for cells, processes, and connections abhinavputhran 2026-03-04 17:48:35 -05:00
• 39343f5f33 docs: document S&R undefined for $dffsr and $dffsre Emil J. Tywoniak 2026-03-04 19:39:41 +01:00
• 0d7a875675 Merge pull request #5512 from YosysHQ/emil/turbo-celltypes Emil J 2026-03-04 14:47:57 +00:00
• 6485a13809 newcelltypes: mark header unstable Emil J. Tywoniak 2026-03-04 15:17:26 +01:00
• 3bc26ff4d0 Merge pull request #5723 from YosysHQ/micko/merge_queue Miodrag Milanović 2026-03-04 13:18:09 +01:00
• 16b1a914f1 Aiger use defines for known ops. nella 2026-03-02 12:24:41 +01:00
• 04822c6660 Readd builtin_ff_cell_types for plugin parity. nella 2026-03-02 12:11:25 +01:00
• b8ee0803ab Remove todo. nella 2026-02-28 18:39:16 +01:00
• 66bd4716cf rtlil use newcelltypes. nella 2026-02-28 18:30:37 +01:00
• cae54a4c7b Aiger use newcelltypes. nella 2026-02-28 18:09:34 +01:00
• 6d4736269b newcelltypes: extend testing Emil J. Tywoniak 2025-11-27 03:32:41 +01:00
• 0284595e9c celltypes: fix absurd eval declarations Emil J. Tywoniak 2025-11-27 03:32:31 +01:00
• 793a3513c6 newcelltypes: use unordered_map Emil J. Tywoniak 2025-11-27 02:53:29 +01:00
• ae10e9e955 pyosys: disable test Emil J. Tywoniak 2025-11-27 01:58:06 +01:00
• 661fcb24cb newcelltypes: fix MSVC build Emil J. Tywoniak 2025-11-26 13:17:24 +01:00
• f594014bef newcelltypes: proper bounds for unit test Emil J. Tywoniak 2025-11-26 13:15:02 +01:00
• 12412d1fa5 register: use newcelltypes Emil J. Tywoniak 2025-11-26 00:53:01 +01:00
• ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users Emil J. Tywoniak 2025-11-26 00:50:41 +01:00
• 5216d32d1b yosys: use newcelltypes for yosys_celltypes Emil J. Tywoniak 2025-11-26 00:47:30 +01:00
• 7a5c303ccd backends: use newcelltypes Emil J. Tywoniak 2025-11-26 00:32:11 +01:00
• c3ed884bc4 drivertools: use newcelltypes Emil J. Tywoniak 2025-11-26 00:16:07 +01:00
• 665b6eeb4a aiger2: add TODO Emil J. Tywoniak 2025-11-26 00:14:12 +01:00
• 4ab22cbb97 abc: use newcelltypes Emil J. Tywoniak 2025-11-26 00:03:53 +01:00
• d91e1c8607 newcelltypes: test against builtin_ff_cell_types Emil J. Tywoniak 2025-11-26 00:03:43 +01:00
• 31b86ebc2e newcelltypes: comment Emil J. Tywoniak 2025-11-25 23:52:30 +01:00
• 8e17fb0266 consteval: use newcelltypes Emil J. Tywoniak 2025-11-25 23:47:56 +01:00
• a0f87dc2d1 modtools: use newcelltypes Emil J. Tywoniak 2025-11-25 23:36:40 +01:00