13 lines
207 B
Plaintext
13 lines
207 B
Plaintext
read_verilog <<EOT
|
|
module test (
|
|
input signed [1:0] n,
|
|
output [3:0] dout
|
|
);
|
|
assign dout = n + 4'sd 4;
|
|
endmodule
|
|
EOT
|
|
|
|
alumacc
|
|
select -assert-count 1 t:$alu
|
|
equiv_opt -assert opt -fine
|