Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}

2019-09-30 12:52:43 +02:00

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achronix

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anlogic

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

common

Missing (* mul2dsp *) for sliceB

2019-09-27 14:21:47 -07:00

coolrunner2

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easic

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ecp5

Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once

2019-09-26 10:45:14 -07:00

efinix

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gowin

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greenpak4

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ice40

Re-order

2019-09-27 14:32:07 -07:00

intel

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sf2

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xilinx

Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}

2019-09-30 12:52:43 +02:00

.gitignore

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