1
0
mirror of synced 2026-01-30 05:44:00 +00:00
Files
YosysHQ.yosys/passes/techmap/simplemap.h
Jannis Harder 7203ba7bc1 Add bitwise $bweqx and $bwmux cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00

1.9 KiB