Krystine Sherwin 064723a1cc example_synth: tidying ...

Adds note on `+/`.
Clarifies that we can't entirely skip loading `cells_sim.v`, and then mentions it again later once we need it.
More on final steps (and synthesis outputs).

2024-01-13 15:46:00 +13:00

..

example_synth.rst

example_synth: tidying

2024-01-13 15:46:00 +13:00

index.rst

TODOs

2023-12-12 12:05:45 +13:00

installation.rst

TODOs

2023-12-12 12:05:45 +13:00

scripting_intro.rst

TODOs

2023-12-12 12:05:45 +13:00