Krystine Sherwin 0cd67ce473 quicklogic: Initial blockram tests ...

Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.

2023-11-30 17:33:13 +01:00

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anlogic

Update tests

2023-06-09 14:41:45 +02:00

common

quicklogic: Initial blockram tests

2023-11-30 17:33:13 +01:00

ecp5

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

efinix

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous

fabulous: Add support for mapping carry chains

2023-02-27 09:50:34 +01:00

gatemate

Update tests

2023-06-09 14:41:45 +02:00

gowin

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

ice40

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

intel_alm

Update tests

2023-06-09 14:41:45 +02:00

machxo2

put back previous test state, due to default change

2023-08-29 10:21:58 +02:00

nexus

Update tests

2023-06-09 14:41:45 +02:00

quicklogic

quicklogic: Initial blockram tests

2023-11-30 17:33:13 +01:00

xilinx

Update tests

2023-06-09 14:41:45 +02:00

run-test.sh

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00