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YosysHQ.yosys/tests/various
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David Shah fa77fb857b Add test for abc9+mince issue 
Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:35:28 +00:00
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.gitignore
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abc9.v
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abc9.ys
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async.sh
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async.v
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attrib05_port_conn.v
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attrib05_port_conn.ys
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attrib07_func_call.v
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attrib07_func_call.ys
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autoname.ys
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bug1496.ys
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bug1531.ys
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bug1614.ys
add testcase for #1614
2020-02-03 21:29:54 +01:00
bug1710.ys
ast: fixes #1710; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
bug1745.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
bug1781.ys
fsm_extract: Initialize celltypes with full design.
2020-03-19 18:51:21 +01:00
chparam.sh
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constcomment.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
constmsk_test.v
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constmsk_test.ys
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constmsk_testmap.v
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deminout_unused.ys
deminout: Don't demote inouts with unused bits
2020-03-04 18:44:38 +00:00
elab_sys_tasks.sv
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elab_sys_tasks.ys
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equiv_opt_multiclock.ys
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exec.ys
Add test for exec command.
2020-03-16 07:52:58 +00:00
gzip_verilog.v.gz
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gzip_verilog.ys
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help.ys
Add "help -all" and "help -celltypes" sanity test
2020-01-28 18:11:34 -08:00
hierarchy_defer.ys
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hierarchy.sh
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ice40_mince_abc9.ys
Add test for abc9+mince issue
2020-03-20 20:35:28 +00:00
logger_error.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_nowarning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warn.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
mem2reg.ys
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
muxcover.ys
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muxpack.v
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muxpack.ys
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peepopt.ys
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pmgen_reduce.ys
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pmux2shiftx.v
Cleanup tests
2020-02-27 10:17:29 -08:00
pmux2shiftx.ys
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reg_wire_error.sv
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reg_wire_error.ys
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run-test.sh
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scratchpad.ys
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script.ys
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sformatf.ys
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shregmap.v
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shregmap.ys
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signext.ys
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specify.v
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
specify.ys
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
src.ys
verilog: add test
2020-03-11 06:51:03 -07:00
submod_extract.ys
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submod.ys
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sv_implicit_ports.sh
sv: More tests for wildcard port connections
2020-02-02 16:12:33 +00:00
svalways.sh
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wreduce.ys
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write_gzip.ys
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