YosysHQ.yosys/techlibs/microchip at 19d32148611707fb71146b8215ca90a469d93b7d - YosysHQ.yosys - Berget Git Service

github.com/YosysHQ.yosys

mirror of synced 2026-04-25 20:02:10 +00:00

Files

History

chunlin min 19d3214861 use output reg instead of additional reg declaration

2024-07-04 14:13:26 -04:00

..

another typo

2024-07-04 10:33:59 -07:00

arith_map.v

changes made to filenames + references

2024-07-04 08:53:41 -07:00

brams_defs.vh

changes made to filenames + references

2024-07-04 08:53:41 -07:00

cells_map.v

changes made to filenames + references

2024-07-04 08:53:41 -07:00

cells_sim.v

use output reg instead of additional reg declaration

2024-07-04 14:13:26 -04:00

LSRAM_map.v

changes made to filenames + references

2024-07-04 08:53:41 -07:00

LSRAM.txt

changes made to filenames + references

2024-07-04 08:53:41 -07:00

Makefile.inc

fixed typos, build with makefile succeeds

2024-07-04 09:33:58 -07:00

microchip_dffopt.cc

changes made to filenames + references

2024-07-04 08:53:41 -07:00

polarfire_dsp_map.v

changes made to filenames + references

2024-07-04 08:53:41 -07:00

synth_microchip.cc

missed a few pf instances

2024-07-04 10:25:15 -07:00

uSRAM_map.v

changes made to filenames + references

2024-07-04 08:53:41 -07:00

uSRAM.txt

changes made to filenames + references

2024-07-04 08:53:41 -07:00