Emil J. Tywoniak ae281720cf tests: remove unstable FPGA synthesis result checks

2025-11-12 11:52:04 +01:00

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aiger

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alumacc

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arch

tests: remove unstable FPGA synthesis result checks

2025-11-12 11:52:04 +01:00

asicworld

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bind

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blif

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bram

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bugpoint

raise_error: don't rely on module ordering in test

2025-09-16 15:47:16 +02:00

cxxrtl

tests: replace CC and gcc with CXX and g++

2025-09-11 16:50:23 +02:00

errors

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fmt

tests: replace CC and gcc with CXX and g++

2025-09-11 16:50:23 +02:00

fsm

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functional

read_verilog: add -relativeshare for synthesis reproducibility testing

2025-09-16 15:47:35 +02:00

hana

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liberty

libparse: fix quoting and negedge in filterlib -verilogsim

2025-11-05 14:13:58 +01:00

lut

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memfile

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memlib

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memories

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opt

Merge pull request #3991 from adrianparvino/alumacc-sign

2025-10-08 13:02:10 +02:00

opt_share

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peepopt

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proc

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pyosys

pyosys: fix regressions from 0.58

2025-10-26 02:21:40 +03:00

realmath

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rpc

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rtlil

Add CONST_FLAG_UNSIZED

2025-11-07 17:45:07 +13:00

sat

fix(parse): #5234 adjust width of rhs according to lhs

2025-09-16 15:24:23 +02:00

select

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share

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sim

Revert sim's cycle_width default back to 10, but keep -width option

2025-10-20 14:40:05 +02:00

simple

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simple_abc9

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smv

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sva

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svinterfaces

tests/svinterfaces: re-chmod test script

2025-10-15 09:49:53 +13:00

svtypes

tests: remove -seq 1 from sat with -tempinduct where possible

2025-09-08 18:04:32 +02:00

techmap

Move global ABC configuration variables into AbcConfig and initialize them properly

2025-11-05 13:56:04 +00:00

tools

tests: replace CC and gcc with CXX and g++

2025-09-11 16:50:23 +02:00

unit

Optimize IdString operations to avoid calling c_str()

2025-11-12 11:52:04 +01:00

various

timeest: Add top ports launching/sampling

2025-11-03 14:21:28 +01:00

verific

Set port_id for Verific PortBus wires

2025-10-23 20:51:53 +00:00

verilog

Merge pull request #5473 from YosysHQ/krys/unsized_params

2025-11-12 07:14:44 +13:00

vloghtb

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xprop

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.gitignore

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gen-tests-makefile.sh

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