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YosysHQ.yosys/frontends
N. Engelhardt 2c847e7efe Merge pull request #1778 from rswarbrick/sv-defines
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
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2020-03-19 08:48:39 -07:00
2019-08-07 11:09:17 -07:00
2020-03-11 22:09:24 +08:00