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YosysHQ.yosys/techlibs/common/simlib.v
Clifford Wolf 95944eb69e make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00

32 KiB