github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-03 06:40:15 +00:00
Code Issues Releases Wiki Activity
Files
2d32c6c4f61052254df32bc7942e4339dd59acaa
YosysHQ.yosys/techlibs/xilinx/cells_sim.v
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers
2015-02-04 16:33:59 +01:00

5.1 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink