Stefan Riesenberger baa3659ea5 ice40: Fix path delay definitions ...

Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.

2023-03-10 10:48:05 +01:00

..

tests

Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

2019-08-12 12:06:45 -07:00

abc9_model.v

Fix icestorm links

2021-06-09 12:39:12 +02:00

arith_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

brams_map.v

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams.txt

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

cells_map.v

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

cells_sim.v

ice40: Fix path delay definitions

2023-03-10 10:48:05 +01:00

dsp_map.v

Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

2019-08-08 12:56:05 -07:00

ff_map.v

ice40: Use dfflegalize.

2020-07-05 05:12:09 +02:00

ice40_braminit.cc

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ice40_opt.cc

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

latches_map.v

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

Makefile.inc

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

spram_map.v

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

spram.txt

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

synth_ice40.cc

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00