24 lines
300 B
Plaintext
24 lines
300 B
Plaintext
ram block $__ICE40_RAM4K_ {
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abits 11;
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widths 2 4 8 16 per_port;
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cost 64;
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option "HAS_BE" 1 {
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byte 1;
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}
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init any;
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port sw "W" {
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option "HAS_BE" 0 {
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width 2 4 8;
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}
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option "HAS_BE" 1 {
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width 16;
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wrbe_separate;
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}
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clock anyedge;
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}
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port sr "R" {
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clock anyedge;
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rden;
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}
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}
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