Eddie Hung aece97024d Fix spacing

2019-04-16 13:16:20 -07:00

..

tests

Improved xilinx "bram1" test

2015-04-09 17:12:12 +02:00

.gitignore

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

arith_map.v

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

brams_bb.v

Added Xilinx bram black-box modules

2015-04-06 08:44:30 +02:00

brams_init.py

Squelch trailing whitespace, including meta-whitespace

2018-03-11 16:03:41 +01:00

brams_map.v

Revert BRAM WRITE_MODE changes.

2019-03-04 09:22:22 -08:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_box.v

Add +/xilinx/cells_box.v containing models for ABC boxes

2019-04-16 11:21:03 -07:00

cells_map.v

Fix cells_map.v some more

2019-04-11 10:48:14 -07:00

cells_sim.v

Revert "Add abc_box_id attribute to MUXF7/F8 cells"

2019-04-16 11:14:59 -07:00

cells_xtra.sh

Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

2019-04-12 09:35:15 -07:00

cells_xtra.v

Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

2019-04-12 09:35:15 -07:00

cells.box

Make cells.box whiteboxes not blackboxes

2019-04-16 12:43:14 -07:00

cells.lut

Fix spacing

2019-04-16 13:16:20 -07:00

drams_map.v

Xilinx DRAMS: RAM64X1D, RAM128X1D

2015-04-09 13:37:07 +02:00

drams.txt

Added memory_bram "make_outreg" feature

2015-04-09 16:08:54 +02:00

ff_map.v

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

lut_map.v

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

Makefile.inc

Add +/xilinx/cells_box.v containing models for ABC boxes

2019-04-16 11:21:03 -07:00

synth_xilinx.cc

read_verilog cells_box.v before techmap

2019-04-16 12:41:56 -07:00