Clifford Wolf f9c096eeda Added support for task and function args in parentheses

2014-10-27 13:21:57 +01:00

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.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

arrays01.v

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carryadd.v

Bugfix in name resolution with generate blocks

2014-01-30 15:01:28 +01:00

constpower.v

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dff_different_styles.v

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fiedler-cooley.v

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forgen01.v

Progress in Verific bindings

2014-03-17 01:56:00 +01:00

forgen02.v

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fsm.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

generate.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

hierarchy.v

Implemented correct handling of signed module parameters

2013-11-24 17:17:21 +01:00

i2c_master_tests.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

loops.v

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macros.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

mem2reg.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

mem_arst.v

Progress in Verific bindings

2014-03-17 01:56:00 +01:00

memory.v

Added multi-dim memory test (requires iverilog git head)

2014-08-12 10:37:47 +02:00

multiplier.v

Added multiplier test case from eda playground

2013-12-18 13:43:53 +01:00

muxtree.v

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omsp_dbg_uart.v

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operators.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

paramods.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

partsel.v

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00

process.v

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realexpr.v

Fixed handling of mixed real/int ternary expressions

2014-06-25 10:05:36 +02:00

repwhile.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

rotate.v

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run-test.sh

Added "make -j{N}" support to "make test"

2014-07-30 19:23:26 +02:00

scopes.v

Improved scope resolution of local regs in Verilog+AST frontend

2014-08-05 12:15:53 +02:00

signedexpr.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

sincos.v

Fix in sincos testbench gen

2013-12-04 09:24:52 +01:00

subbytes.v

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task_func.v

Added support for task and function args in parentheses

2014-10-27 13:21:57 +01:00

undef_eqx_nex.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

usb_phy_tests.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

values.v

Replaced RTLIL::Const::str with generic decoder method

2013-12-04 14:14:05 +01:00

vloghammer.v

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