github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-07 09:07:09 +00:00
Code Issues Releases Wiki Activity
Files
5ab59cd59ee90abc4b6991486854dbe4c3f4d0a4
YosysHQ.yosys/kernel/rtlil.cc
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00

106 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink