Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. ...

Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.

2025-07-03 20:51:12 -06:00

..

source

verilog: add support for SystemVerilog string literals.

2025-07-03 20:51:12 -06:00

tests

docs: Fix macro_commands

2024-05-10 09:51:37 +12:00

util

Docs: Render cell titles

2024-10-15 07:35:42 +13:00

.gitignore

Docs: Preliminary autocellgroup usage

2024-10-15 07:26:04 +13:00

Makefile

Makefile: Combine gen_images and gen_examples

2024-10-17 07:12:34 +13:00