Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. ...

Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.

2025-07-03 20:51:12 -06:00

..

_downloads

Replace 010 and 012 with pdf

2023-10-30 10:34:30 +13:00

_images

mk: Fall back to cp if rsync is not available

2025-03-24 18:06:17 +01:00

_static

Docs: Switch to furo-ys

2024-10-15 07:24:14 +13:00

appendix

docs: several small documentation fixes.

2025-05-29 21:26:28 -06:00

cell

docs: mention related effects for multiplexers in the cell library.

2025-05-30 21:43:33 -06:00

code_examples

Reinstate #4768

2025-04-08 11:58:05 +12:00

getting_started

Fix Docs issues for offline pdf builds #4777

2025-03-15 12:14:09 +13:00

using_yosys

abc.rst: Clarify larger-but-slower

2025-05-31 09:10:27 +12:00

yosys_internals

verilog: add support for SystemVerilog string literals.

2025-07-03 20:51:12 -06:00

bib.rst

Add todo

2023-12-13 10:15:51 +13:00

cell_index.rst

Docs: Comments from @jix

2024-10-15 07:37:20 +13:00

cmd_ref.rst

Docs: Rename source/temp to source/generated

2024-04-15 10:13:22 +12:00

conf.py

Release version 0.54

2025-06-09 07:23:54 +02:00

index.rst

Docs: Remove restructure note

2025-01-06 11:08:00 +13:00

introduction.rst

Docs: Fix nested list

2024-11-05 13:48:48 +13:00

literature.bib

Rst docs conversion (#3496)

2022-11-15 12:55:22 +01:00

requirements.txt

Docs: Switch to furo-ys

2024-10-15 07:24:14 +13:00