YosysHQ.yosys/techlibs/common/simcells.v at 6e152f7aa1a5752eae6e7bd8a67dfce2bd0d64f6 - YosysHQ.yosys - Berget Git Service

github.com/YosysHQ.yosys

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Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells

2016-10-14 12:33:56 +02:00

30 KiB

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